A million spiking-neuron integrated circuit with a scalable communication network and interface

  title={A million spiking-neuron integrated circuit with a scalable communication network and interface},
  author={Paul A. Merolla and John V. Arthur and Rodrigo Alvarez-Icaza and Andrew S. Cassidy and Jun Sawada and Filipp Akopyan and Bryan L. Jackson and Nabil Imam and Chen Guo and Yutaka Y. Nakamura and Bernard Brezzo and Ivan Vo and Steven K. Esser and Rathinakumar Appuswamy and Brian Taba and Arnon Amir and Myron Flickner and William P. Risk and Rajit Manohar and Dharmendra S. Modha},
Inspired by the brain’s structure, we have developed an efficient, scalable, and flexible non–von Neumann architecture that leverages contemporary silicon technology. To demonstrate, we built a 5.4-billion-transistor chip with 4096 neurosynaptic cores interconnected via an intrachip network that integrates 1 million programmable spiking neurons and 256 million configurable synapses. Chips can be tiled in two dimensions via an interchip communication interface, seamlessly scaling the… CONTINUE READING
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