A method to determine the lateral trap position in ultra-scaled MOSFETs

Abstract

We propose the new method for the evaluation of the lateral trap position in ultra-scaled MOSFETs with a precision of less than 1nm. The method is based on a simple analytical model which links the surface potential in the presence of a discrete trap and the drain voltage. To verify this analytical approach we employ the TCAD data obtained on test both nand p-MOSFETs with different channel lengths.

4 Figures and Tables

Cite this paper

@inproceedings{Illarionov2013AMT, title={A method to determine the lateral trap position in ultra-scaled MOSFETs}, author={Yu.Yu. Illarionov and S. E. Tyaginov and M. Bina and Tibor Grasser}, year={2013} }