A memory efficient array architecture for full-search block matching algorithm

@inproceedings{Moshnyaga1997AME,
  title={A memory efficient array architecture for full-search block matching algorithm},
  author={Vasily G. Moshnyaga and Keikichi Tamaru},
  booktitle={ICASSP},
  year={1997}
}
This paper proposes a novel array architecture for full-search block matching motion estimation. The design efforts are focused on transforming the array computation in a way that minimizes the memory and I/O costs while satisfying the highest throughput requirements. Compared with the existing architectures, this one ensures feasible solutions for the HDTV picture format with twice lower memory requirements, minimal I/O pin count and 100% processor utilization. The architecture features… CONTINUE READING
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