A memory aware high level synthesis tool


We introduce a new approach to take into account the memory architecture and the memory mapping in high-level synthesis for data intensive applications. We formalize the memory mapping as a set of constraints for the synthesis, and defined a memory constraint graph and an accessibility criterion to be used in the scheduling step. We use a memory mapping… (More)
DOI: 10.1109/ISVLSI.2004.1339557

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