A low-voltage alterable EEPROM with metal—oxide-nitride—oxide—semiconductor (MONOS) structures

@article{Suzuki1983ALA,
  title={A low-voltage alterable EEPROM with metal\&\#8212;oxide-nitride\&\#8212;oxide\&\#8212;semiconductor (MONOS) structures},
  author={Eiichi Suzuki and Hisato Hiraishi and K. Ishii and Yutaka Hayashi},
  journal={IEEE Transactions on Electron Devices},
  year={1983},
  volume={30},
  pages={122-128}
}
Theoretical and experimental investigations to obtain lower voltage electrically erasable and programmable ROM's (EEPROM's) than conventional devices have been performed. The scaled-down metal-oxide-nitride-oxide-semiconductor (MONOS) structure is proposed to realize an extremely low-voltage programmable device. The proposed scaled-down MONOS devices enjoy several advantages over MNOS devices, e.g., enlargement of the memory window, elimination of degradation phenomena, and drastic improvement… 

Figures from this paper

A low voltage SONOS nonvolatile semiconductor memory technology
The triple-dielectric polysilicon-blocking oxide-silicon nitride-tunnel oxide-silicon (SONOS) structure is an attractive candidate for high density E/sup 2/PROMs suitable for semiconductor disks and
A novel MONOS nonvolatile memory device ensuring 10-year data retention after 10/sup 7/ erase/write cycles
A highly reliable nonvolatile memory device suitable for high-density electrically erasable and programmable read only memories (EEPROMs) is described. A metal-oxide-nitride-oxide-semiconductor
A low voltage SONOS nonvolatile semiconductor memory technology
The triple dielectric SONOS (polysilicon-blocking oxide-silicon nitridetunnel oxide-silicon) structure is an attractive candidate for high density E/sup 2/PROM's suitable for semiconductor disks and
Reliability study of thin inter-poly dielectrics for non-volatile memory application
The key factors which dominate the leakage current in poly-oxide are reviewed, and intrinsic limitations in thinner poly-oxide to device application are investigated. The ON (oxide-nitride-oxide)
Hot Carrier Design Considerations in MOS Nonvolatile Memories
Floating-gate type nonvolatile semiconductor memories (NVSMs) were first introduced and applied by Kahng and Sze in 1967 [1]. The metal-nitride-oxide-silicon (MNOS) structure was first reported by
Amorphous silicon TFT based non-volatile memory
  • Biology
  • 2011
TLDR
This chapter describes the structure and principle of operation of the a-Si TFT based floating gate non-volatile memory, and presents a new nonvolatility memory TFT structure that overcomes the limitations associated the floating gate device.
High performance sub-0.25 /spl mu/m devices using ultrathin oxide-nitride-oxide gate dielectric formed with low pressure oxidation and chemical vapor deposition
An ultra-thin, high reliability oxide-nitride-oxide (ONO) gate dielectric was formed using low pressure oxidation and chemical vapor deposition. A sub-0.25 /spl mu/m device with high performance was
...
1
2
3
4
5
...

References

SHOWING 1-10 OF 31 REFERENCES
FCAT—A low-voltage high-speed alterable n-channel nonvolatile memory device
The structure and principles of a new nonvolatile charge storage device are described. The Floating Si-gate Channel Corner Avalanche Transition (FCAT) memory device is an n-channel MOS transistor
Threshold-alterable Si-gate MOS devices
  • P.C.Y. Chen
  • Engineering
    IEEE Transactions on Electron Devices
  • 1977
An electrically threshold-alterable n-channel MOS device with polysilicon gate is experimentally realized by employing a polysilicon-oxynitride-nitride-oxide-silicon (SONOS) structure. Because of
Electrically-alterable memory using a dual electron injector structure
A novel type of electrically-alterable memory which uses the phenomenon of enhanced electron injection into SiO2from Si-rich SiO2to charge or discharge a floating polycrystalline Si storage layer in
Low-voltage alterable EAROM cells with nitride-barrier avalanche-injection MIS (NAMIS)
Design and characteristics of NAMIS-EAROM cells alterable with voltages of about 10 V are demonstrated. The NAMIS cell employs a very thin silicon nitride film grown by direct thermal nitridation of
Electrically alterable read-only memory cell with graded energy band-gap insulator
Low voltage alterability and excellent memory retention have been obtained with a novel EAROM cell that has a graded energy band-gap film as the first insulator of a Floating-Gate type memory. The
Atmos—An electrically reprogrammable read-only memory device
An adjustable threshold MOS (Atmos) transistor is described that can be used as an electrically reprogrammable read-only memory by changing the charge content of a floating polysilicon gate. This
Theory of MNOS memory transistor
  • J. Chang
  • Physics
    IEEE Transactions on Electron Devices
  • 1977
A theory on the switching behavior of the metal-Si3N4-SiO2-semiconductor (MNOS) memory transistor is presented which is consistent with the experimentally observed facts. The theory treats the
A model of degradation mechanisms in metal‐nitride‐oxide‐semiconductor structures
The degradation of a metal‐nitride‐oxide‐semiconductor (MNOS) structure has been investigated using p‐channel MNOS transistors with a relatively thick oxide layer. Significant degradation effects,
A 1024-bit MNOS RAM using avalanche-tunnel injection
TLDR
MNOS memory cells which consist of one MNOS transistor and two MOS transistors are incorporated into a fully decoded 1024-word by 1-bit random access memory (RAM) with nonvolatility by introducing a novel mode of write operation.
Electrically alterable avalanche-injection-type MOS READ-ONLY memory with stacked-gate structure
Design theory and experimental results of the WRITE and ERASE properties of a rewritable and nonvolatile avalanche-injection-type memory are reported. The memory transistor has the stacked-gate
...
1
2
3
4
...