A low-power dual threshold voltage-voltage scaling technique for domino logic circuits

Abstract

As domino logic design offers smaller area and higher speed than complementary CMOS design, it has been very commonly used for high-performance processors; however, the average power consumption of the domino circuits is larger than that of the static circuit. This power dissipation problem needs to be solved for the domino circuits. The power consumption… (More)

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Cite this paper

@article{Arun2012ALD, title={A low-power dual threshold voltage-voltage scaling technique for domino logic circuits}, author={Pratibha Arun and S. Ramasamy}, journal={2012 Third International Conference on Computing, Communication and Networking Technologies (ICCCNT'12)}, year={2012}, pages={1-6} }