A low-power dual-clock strategy for digital circuits of EPC Gen2 RFID tag

Abstract

Power consumption is critical to the performance of EPC Gen2 RFID tags. System clock frequency of tags should be as low as possible to reduce the power consumption and still conform to the protocol. This paper analyses the impact of different clock strategies on digital circuits of EPC Gen2 tag. An error shift approach is proposed to reduce the backscatter… (More)

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Cite this paper

@article{Luo2009ALD, title={A low-power dual-clock strategy for digital circuits of EPC Gen2 RFID tag}, author={Qiasi Luo and Li Guo and Qing Li and Gang Zhang and Junyu Wang}, journal={2009 IEEE International Conference on RFID}, year={2009}, pages={7-14} }