A low power and high speed level shifter with delay circuits

@article{Yaoyao2013ALP,
  title={A low power and high speed level shifter with delay circuits},
  author={Jia Yaoyao and Zhang Leiming and Chen Yiwen and Fang Jian and Zhang Bo},
  journal={2013 International Conference on Communications, Circuits and Systems (ICCCAS)},
  year={2013},
  volume={2},
  pages={378-381}
}
A level shifter with low power and high speed characteristics is proposed, which is simulated in the 0.18μm standard CMOS process. The proposed level shifter minimizes the contention problem between the pull-up PMOS transistors and pull-down NMOS transistors by using delay circuits. Compared with the conventional level shifter, the simulation results show that the proposed level shifter can achieve about 42.8% power reduction, 6.7% falling time of output level signal saving and 20.0% high-to… CONTINUE READING

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