A low-power VLSI architecture for a shared-memory FFT processor with a mixed-radix algorithm and a simple memory control scheme

@article{Lee2006ALV,
  title={A low-power VLSI architecture for a shared-memory FFT processor with a mixed-radix algorithm and a simple memory control scheme},
  author={Shuenn-Yuh Lee and Chia-Chyang Chen and Shyh-Chyang Lee and Chih-Jen Cheng},
  journal={2006 IEEE International Symposium on Circuits and Systems},
  year={2006},
  pages={4 pp.-160}
}
A simple addressing scheme for pipeline MDC shared-memory architecture with mixed-radix algorithm is proposed. It can provide a simple control circuit for memory addressing generation, and the mixed-radix butterfly sequence can be automatically generated by way of simple counter. In addition, for the N-point FFT processor, only N/8 coefficients should be stored in the VLSI implementation, therefore, the ROM size and the FFT processor area are reduced. According to the simple control scheme and… CONTINUE READING