A low-power DSP core architecture for low bitrate speech codec

Abstract

.A VLSI irlllJl(~rll(~~lt;l.ti(.J~l of ;L low~~onv~r DSF’ is tloscribed. which is d<YliCilt(-d to the G.723.1 low bitr;it.f\ speech c:oclcc X numhcr of sophistiwtrd DSP microarcliitecturcs are dv\:isccl mainly 011 (lllill multiply ilC(‘llmulators, rounding and sntura.tion mechanisms. i1.11c1 t,wo-banked on-chip rrwmory. Thtb ~JIXJ~OSNI DSF’ ilrchitect~iw 1la.s lwm illtegridcd in tlitx r0t.a.l area of 7.7$? IIIIn2 by IIsing R 0.3ZpIIl ChIOS tPchIl010g~. which (‘ill1 operate ilt lO.\IHz with the dissilJ;ltion of 451n~V froII1 a. sir&> 3i7 sil~~~~ly.

DOI: 10.1109/ICASSP.1998.678187

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Cite this paper

@inproceedings{Okuhata1998ALD, title={A low-power DSP core architecture for low bitrate speech codec}, author={Hiroyuki Okuhata and Morgan Hirosuke Miki and Takao Onoye and Isao Shirakawa}, booktitle={ICASSP}, year={1998} }