A low-power Content-Addressable Memory based on clustered-sparse networks

@article{Jarollahi2013ALC,
  title={A low-power Content-Addressable Memory based on clustered-sparse networks},
  author={Hooman Jarollahi and Vincent Gripon and Naoya Onizawa and Warren J. Gross},
  journal={2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors},
  year={2013},
  pages={305-308}
}
  • Hooman Jarollahi, Vincent Gripon, W. Gross
  • Published 18 February 2013
  • Computer Science
  • 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors
A low-power Content-Addressable Memory (CAM) is introduced employing a new mechanism for associativity between the input tags and the corresponding address of the output data. The proposed architecture is based on a recently developed clustered-sparse network using binary-weighted connections that on-average will eliminate most of the parallel comparisons performed during a search. Therefore, the dynamic energy consumption of the proposed design is significantly lower compared to that of a… 
View on IEEE
arxiv.org
27 Citations
Background Citations
10
Methods Citations
8

Figures and Tables from this paper

27 Citations

Citation Type

Citation Type

Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks
TLDR
A low-power content-addressable memory (CAM) employing a new algorithm for associativity between the input tag and the corresponding address of the output data is proposed, based on a recently developed sparse clustered network using binary connections.
Content Addressable Memory Architecture based on Sparse Clustered Networks
TLDR
The main aim of this project is to design a low-power Content-Addressable Memory by applying an algorithm for associativity between the input tag and the address of the corresponding output data by using a recently developed sparse clustered networks using binary connections.
A Survey on Design of Content Addressable Memories
We survey the recent developments in the design of large-capacity content addressable memory (CAM). A CAM is a memory unit that process single clock cycle content matching instead of addresses using…
Low power CAM design using modified SCN based classifier
TLDR
The proposed architecture is based on a recently developed sparse clustered network which eliminates most of the parallel comparisons performed during a search operation.
Low-power content addressable memory (CAM) array for mobile devices
A high speed and low power content-addressable memory(CAM) using pipelined scheme
TLDR
A novel technique to design high performance Content-addressable memories (CAMs), with lower power and latency as compared to other similar structures, by distributing single matching operation into several segments for different search-line registers.
Implementation of SCN Based Content Addressable Memory
TLDR
The proposed CAM is based on a recently developed sparse clustered network (SCN) that onaverage will eliminate most of the parallel comparisons performed during a search, suitable for low-power applications, where frequent and parallel look-up operations are required.
A fully parallel content addressable memory design using multi-bank structure
TLDR
A novel technique to reduce the power and latency in content-addressable memories (CAMs) by discontinue the unnecessarily subsequent search-line precharge process based on pipelined matchline searching operation and improving the speed by implementing split-path match-line circuit into each match- line segment.
A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture
This paper presents algorithm, architecture, and fabrication results of a nonvolatile context-driven search engine that reduces energy consumption as well as computational delay compared to classical…
High-Throughput Low-Energy Self-Timed CAM Based on Reordered Overlapped Search Mechanism
TLDR
A reordered overlapped search mechanism for high-throughput low-energy content-addressable memories (CAMs) is introduced to increase throughput by asynchronously initiating second-stage searches on the unused match lines as soon as a first-stage search is complete.
...
...

References

SHOWING 1-10 OF 19 REFERENCES
A low-power precomputation-based fully parallel content-addressable memory
TLDR
A novel VLSI architecture for a fully parallel precomputation-based content-addressable memory (PB-CAM) with low-power, low-cost, and low-voltage features and adopts the static pseudo-nMOS circuit design to improve system performance.
Low Power Design of Precomputation-Based Content-Addressable Memory
TLDR
Through mathematical analysis, it is found that the proposed Block-xor PB-CAM system can achieve greater power reduction without the need for a special CAM cell design and is more flexible and adaptive for general designs.
Content-addressable memory (CAM) circuits and architectures: a tutorial and survey
TLDR
This paper surveys recent developments in the design of large-capacity content-addressable memory (CAM) and reviews CAM-design techniques at the circuit level and at the architectural level.
Hybrid-Type CAM Design for Both Power and Performance Efficiency
TLDR
Because the hybrid-type CAM provides a fast pull-down path to speed up the lightweight match line discharge, the search performance of the design is even better than that of the traditional NOR- type CAM.
High-Throughput Low-Energy Content-Addressable Memory Based on Self-Timed Overlapped Search Mechanism
TLDR
A self- Timed overlapped overlapped search mechanism for high-throughput content-addressable memories (CAMs) with low search energy is introduced using a self-timed word circuit that is independently controlled by a locally generated control signal, reducing the power dissipation of global clocking.
A 128×128b high-speed wide-and match-line content addressable memory in 32nm CMOS
TLDR
A high-speed 16b wide dynamic AND match-line, combined with a fully static search-line and swapped XOR CAM cell simulations show a 49% reduction of search energy at iso-search delay of 145ps over an optimized high-performance conventional NOR-type CAM design, enabling 1.07fJ/bit/search operation.
A 65 nm 0.165 fJ/Bit/Search 256 $\,\times\,$144 TCAM Macro Design for IPv6 Lookup Tables
TLDR
This work presents a novel 65 nm energy-efficient TCAM macro design for IPv6 applications using UMC 65 nm CMOS technology, and the experimental results demonstrate a leakage power reduction of 19.3% and an energy metric of the TCAM Macro of 0.165 fJ/bit/search.
An AND-type match-line scheme for energy-efficient content addressable memories
TLDR
An AND-type match-line scheme is fabricated in a 0.8V CMOS process and achieves a faster search time and a 20% energy reduction compared with NOR designs.
Architecture and implementation of an associative memory using sparse clustered networks
TLDR
A proof-of-concept hardware implementation of a novel algorithm based on sparse clustered neural networks that achieves nearly optimal efficiency and large diversity is presented.
Design of multi-field IPv6 packet classifiers using ternary CAMs
TLDR
This paper intends to design a novel packet classification engine capable of simultaneously processing multi-field searching, especially for the IPv6 packets with relative longer addresses (128 bits).
...
...