Corpus ID: 17757602

A low power ASIP for precision configurable FFT processing

@article{Bo2012ALP,
  title={A low power ASIP for precision configurable FFT processing},
  author={Yifan Bo and Jun Han and Yao Zou and Xiaoyang Zeng},
  journal={Proceedings of The 2012 Asia Pacific Signal and Information Processing Association Annual Summit and Conference},
  year={2012},
  pages={1-4}
}
  • Yifan Bo, Jun Han, +1 author Xiaoyang Zeng
  • Published in
    Proceedings of The Asia…
    2012
  • Computer Science
  • Fast Fourier transformation (FFT) is a key operation in digital communication systems. Different communication standards require various FFT length and precision. In this paper, we present a low power Application-Specific Instruction-set Processor (ASIP) for variable length (16-point-4096-point) and bit precision (8-bit - 16-bit) to meet different requirements. We use scalable multipliers to construct the butterfly unit, which support both 8-bit and16-bit operation. The order of butterfly… CONTINUE READING

    Create an AI-powered research feed to stay up to date with new papers like this posted to ArXiv

    Citations

    Publications citing this paper.
    SHOWING 1-4 OF 4 CITATIONS

    Rapid prototype and implementation of a high-throughput and flexible FFT ASIP based on LISA 2.0

    VIEW 4 EXCERPTS
    CITES METHODS & BACKGROUND
    HIGHLY INFLUENCED

    A digital processor architecture for combined EEG/EMG falling risk prediction

    VIEW 1 EXCERPT

    A highly scalable vector oriented ASIP-based multi-standard digital receiver

    References

    Publications referenced by this paper.
    SHOWING 1-10 OF 14 REFERENCES

    A high throughput configurable FFT processor for WLAN and WiMax protocols

    A high throughput configurable FFT processor for WLAN and WiMax protocols

    • R. Netto andJ.L. Guntzel
    • Programmable Logic (SPL), 2012 VIII Southern Conf. on , pp.1-5, March 2012
    • 2012
    VIEW 1 EXCERPT

    da Costa andS . Ghissoni , " Reducing power consumption in FFT architectures by using heuristicbased algorithms for the ordering of the twiddle factors , " Circuits and Syst

    • E. A. C. A. G. da Luz
    • 2012

    A Low Area Pipelined FFT Processor for OFDM-Based Systems

    • Qihui Zhang, Nan Meng
    • Computer Science
    • 2009 5th International Conference on Wireless Communications, Networking and Mobile Computing
    • 2009
    VIEW 1 EXCERPT

    A context aware wireless body area network (BAN)

    VIEW 2 EXCERPTS

    The design of a reconfigurable continuous-flow mixed-radix FFT processor

    VIEW 1 EXCERPT

    Balanced Binary-Tree Decomposition for Area-Efficient Pipelined FFT Processing

    VIEW 2 EXCERPTS