A low-noise, 8.95–11GHz all-digital frequency synthesizer with a metastability-free time-to-digital converter and a sleepy counter in 65nm CMOS

A low-noise 8.95~11GHz all digital frequency synthesizer (ADPLL) with a metastability-free first-order noise shaping time-to-digital converter (TDC) and a high frequency resolution digitally controlled oscillator (DCO) is presented. An input stage for TDC is proposed to solve the problem of metastability and a specific technique is used to power down the… CONTINUE READING