A low leakage 9t sram cell for ultra-low power operation

@inproceedings{Lin2008ALL,
  title={A low leakage 9t sram cell for ultra-low power operation},
  author={Sheng Lin and Yong-Bin Kim and Fabrizio Lombardi},
  booktitle={ACM Great Lakes Symposium on VLSI},
  year={2008}
}
This paper presents the design and evaluation of a new SRAM cell made of nine transistors (9T). The proposed 9T cell utilizes a scheme with separate read and write wordlines; it is shown that the 9T cell achieves improvements in power dissipation, performance and stability compared with previous designs (that require 10T and 8T) for low-power operation. The 9T scheme is amenable to small feature sizes as encountered in the deep sub-micron/nano ranges of CMOS technology. 
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