A low-leakage 2.5GHz skewed CMOS 32b adder for nanometer CMOS technologies

Abstract

A 32b parallel prefix adder demonstrates leakage-current-reduction capabilities of skewed CMOS logic. Sub-100nA leakage currents and single-cycle activation from standby mode is achieved using multi-tox logic gates in 90nm CMOS technology. The data path contains improved sense amplifier-based flip-flops and skewed CMOS logic adapted latches. 

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@article{Arnim2005AL2, title={A low-leakage 2.5GHz skewed CMOS 32b adder for nanometer CMOS technologies}, author={Klaus von Arnim and P. Seegebrecht and Roberta Thewes and Christian Pacha}, journal={ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.}, year={2005}, pages={380-605 Vol. 1} }