A low-jitter wideband multiphase PLL in 90nm SOI CMOS technology

@article{Kossel2005ALW,
  title={A low-jitter wideband multiphase PLL in 90nm SOI CMOS technology},
  author={M. Kossel and Peter Buchmann and Christian Menolfi and Thomas Morf and Thomas Toifl and Martin Schmatz},
  journal={ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.},
  year={2005},
  pages={414-415 Vol. 1}
}
A multiphase PLL, implemented in 90nm SOI CMOS, covers a frequency range from 4.3 to 7.4GHz at a supply voltage of 1V. The ring oscillator-based PLL shows an in-band phase noise of up to -113dBc/Hz at 1 MHz offset and a supply noise rejection of 0.23%delay/%supply due to the rigorous application of CML-type circuit topologies combined with replica biasing. 

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