A low-cost built-in error correction circuit design for STT-MRAM reliability improvement


Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) possesses various merits, such as non-volatility, low power and high speed. It has been considered as a promising non-volatile memory candidate used universally in logic computing, cache and storage applications. However it suffers from serious reliability issues compared with conventional schemes, especially in deep submicron technologies. This paper proposes a low-cost built-in error correction circuit to improve STT-MRAM reliability. Its straightforward ''XOR'' encoder and one-step majority-voting decoder provide much lower area and higher speed compared with conventional ECCs, and its modular codec structure allows adaptive error correction capability according to the system requirement. Simulation based on a compact STT model and STMicroelectronics 40 nm technology node was carried out to confirm its effectiveness. Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) promises various merits such as non-volatility, low power, infinite endurance and high speed [1–3]. It has been expected as an emerging ''universal memory'' for logic computing, cache and storage applications, and considered to be able to replace all other types of memories [4–6]. These advantageous features attract much attention of R&D, a number of pre-industrial prototypes have been demonstrated since 2005 [4,5] and one expects to widely commercialize it in the next few years. However, STT-MRAM suffers from serious reliability challenges due to its intrinsic stochas-tic switching mechanism and the process voltage temperature (PVT) variations etc. [7–9], especially as technology scales. Fig. 1 shows its raw bit error rate (BER) performance under several typical technology nodes. Though many circuit design techniques and strategies, such as self-enable switching, advanced thin film techniques and sensing circuits [9–11], have been proposed recently to improve its reliability, the final BER is still high (>10 À5) and insufficient for reliable usages. Therefore, STT-MRAM needs error correction code or circuit (ECC) to guarantee its reliability as conventional memories (e.g. SRAM and Flash). Triple Modular Redundancy Code (TMRC) and Hamming code are two popular error correction schemes used widely in logic computing and cache [12,13]. However, Hamming provides very limited error correction capability t (t = 1), which cannot address the particularly high BER of STT-MRAM, while TMRC leads to large area redundancy and high power. Other multi-bits error correction ECCs, such as Bose–Chau-dhuri–Hocquenghem (BCH) code and Low-Density Parity-Check (LDPC) code [12], are usually used in mass storage applications and they are rarely employed for logic computing and cache due to their high complexities and decoding latencies. Thereby, …

DOI: 10.1016/j.microrel.2013.07.036

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@article{Kang2013ALB, title={A low-cost built-in error correction circuit design for STT-MRAM reliability improvement}, author={Wang Kang and Weisheng Zhao and Zhaohao Wang and Yue Zhang and Jacques-Olivier Klein and Youguang Zhang and Claude Chappert and Dafine Ravelosona}, journal={Microelectronics Reliability}, year={2013}, volume={53}, pages={1224-1229} }