A jitter characterization system using a component-invariant Vernier delay line

@article{Chan2004AJC,
  title={A jitter characterization system using a component-invariant Vernier delay line},
  author={Antonio H. Chan and Gordon W. Roberts},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2004},
  volume={12},
  pages={79-95}
}
Jitter characterization has become significantly more important for systems running at multigigahertz data rates. Time and frequency domain characterization of jitter is thus a crucial element for system specification testing. Time domain jitter measurement on a data signal with subgate timing resolution can be achieved using two delay chains feeding into the clock and datalines of a series of D-latches known as a Vernier delay line (VDL). An important drawback to the VDL structure is that its… CONTINUE READING
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