A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array

Abstract

At most advanced technology nodes, Field Programmable Gate Arrays (FPGA) present great advantages compared to more conventional processor architectures; their natural regularity, modularity and inherent reliability due to duplicated identical tiles provide a solution to overcome new technologies with increasing variability. However, FPGA market is still limited by power efficiency issue, due to two coordinated factors like interconnection-dominated design and large usage of memories, computation being performed thanks to Look-Up-Table (LUT). In this paper, we propose a solution to improve the performance and reduce the power consumption of LUT in FPGA using CBRAM-based structures. Our proposed design shows significant improvement compared to the traditional SRAM-based FPGA in: a) critical delay is reduced by ∼23% due to compact structure (1T-2R) and b) power gain by reduction in static power consumption by ∼18%.

DOI: 10.1109/ISCAS.2013.6572372

8 Figures and Tables

Cite this paper

@inproceedings{Onkaraiah2013AHC, title={A hybrid CBRAM/CMOS Look-Up-Table structure for improving performance efficiency of Field-Programmable-Gate-Array}, author={Santhosh Onkaraiah and Ogun Turkyilmaz and Marina Reyboz and Fabien Clermidy and Elisa Vianello and Jean Michel Portal and Christophe Muller}, booktitle={ISCAS}, year={2013} }