A highly parallel Turbo Product Code decoder without interleaving resource

@article{Leroux2008AHP,
  title={A highly parallel Turbo Product Code decoder without interleaving resource},
  author={Camille Leroux and Christophe J{\'e}go and Patrick Adde and Michel J{\'e}z{\'e}quel and Deepak Gupta},
  journal={2008 IEEE Workshop on Signal Processing Systems},
  year={2008},
  pages={1-6}
}
This article presents an innovative turbo product code (TPC) decoder architecture without any interleaving resource. This architecture includes a full-parallel SISO decoder able to process n symbols in one clock period. Syntheses show the better efficiency of such an architecture compared with existing previous solutions. Considering a 6-iteration turbo decoder of a (32,26)2 BCH product code, synthetized in a 90 nm CMOS technology, the resulting information throughput is 2.5 Gb/s with an area… CONTINUE READING

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