A high-speed layered min-sum LDPC decoder for error correction of NAND Flash memories

@article{Kim2011AHL,
  title={A high-speed layered min-sum LDPC decoder for error correction of NAND Flash memories},
  author={Jonghong Kim and Junhee Cho and Wonyong Sung},
  journal={2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)},
  year={2011},
  pages={1-4}
}
NAND Flash memory controllers need to equip strong and high speed error correction blocks as the cell size scales down and multi-level cell technology is employed. We have developed an LDPC (low-density parity-check) decoder for NAND Flash memory error correction, and implemented it using a layered min-sum decoding architecture. A shortened (69615, 66897) regular EG-LDPC code that has the code rate of 96% is used, which has a good minimum distance and quasi-cyclic structure. In order to… CONTINUE READING
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