A high speed binary floating point multiplier using Dadda algorithm

@article{Jeevan2013AHS,
  title={A high speed binary floating point multiplier using Dadda algorithm},
  author={B. Jeevan and S. Narender and C. V. Krishna Reddy and Kosaraju Sivani},
  journal={2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s)},
  year={2013},
  pages={455-460}
}
This paper presents a high speed binary floating point multiplier based on Dadda Algorithm. To improve speed multiplication of mantissa is done using Dadda multiplier replacing Carry Save Multiplier. The design achieves high speed with maximum frequency of 526 MHz compared to existing floating point multipliers. The floating point multiplier is developed to handle the underflow and overflow cases. To give more precision, rounding is not implemented for mantissa multiplication. The multiplier is… CONTINUE READING
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