A high-speed FFT processor for OFDM systems

  title={A high-speed FFT processor for OFDM systems},
  author={Byung S. Son and Byung G. Jo and Myung Hoon Sunwoo and Yong Serk Kim},
This paper proposes a high-speed FFT processor for orthogonal frequency-division multiplexing (OFDM) systems. The proposed architecture uses a single-memory for a small hardware size and uses a radix-4 algorithm for high speed. Its memory is partitioned into four banks for high-speed computation. It uses an in-place memory strategy that stores butterfly outputs in the same memory location used by butterfly inputs. The architecture has been modeled by VHDL and logic synthesis has been performed… CONTINUE READING
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Publications referenced by this paper.
Showing 1-10 of 14 references

A low power, high performance, 1024-point FFT processor,

B. M. Bass
IEEE J. Solid-State Circuits, • 1999
View 1 Excerpt

A pipelined sharedmemory architecture for FFT procesror

SI L. Jia, Y. Gao, H. Tenhunm
Proc . IEEE 42 nd Midwest Symp . Circuits Syst . • 1999

Chanp,, “A novel DHT-based FFT/IFFT processor for ADSL transceivers,

C.H.C.L. Wang
in Proc. IEEE Int. Symp. Circuits Sysr., • 1999

Tenhunm, “A pipelined sharedmemory architecture for FFT procesror,

SI L. Jia, Y. Gao
in Proc. IEEE 42nd Midwest Symp. Circuits Syst., • 1999