A high-resolution all-digital phase-locked loop with its application to built-in speed grading for memory

@article{Hsu2008AHA,
  title={A high-resolution all-digital phase-locked loop with its application to built-in speed grading for memory},
  author={Hsuan-Jung Hsu and Chun-Chieh Tu and Shi-Yu Huang},
  journal={2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT)},
  year={2008},
  pages={267-270}
}
In this paper we present a high-resolution and wide-range all-digital phase-locked loop (ADPLL), which is suitable to function as a clock generator. The digitally controlled oscillator (DCO) is able to operate from 70 to 725 MHz and achieves 5.2ps resolution. The phase-frequency detector (PFD) is designed using a latch-based sense amplifier, leading to a nearly perfect PFD that is able to resolve a phase difference as minute as only 1ps. In addition, we use this ADPLL as a vehicle to perform… CONTINUE READING
Highly Cited
This paper has 20 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 15 extracted citations

References

Publications referenced by this paper.
Showing 1-6 of 6 references

The design of an all-digital phase locked loop with small DCO hardware and fast phase lock

  • J. -S Chiang, K. -Y Chen
  • IEEE Trans. Circuits Syst. II, vol. 46, pp. 945…
  • 1999
2 Excerpts

Similar Papers

Loading similar papers…