A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC

@article{Geerts2000AHM,
  title={A high-performance multibit /spl Delta//spl Sigma/ CMOS ADC},
  author={Y. Geerts and M. Steyaert and W. Sansen},
  journal={IEEE Journal of Solid-State Circuits},
  year={2000},
  volume={35},
  pages={1829-1840}
}
The design of a multibit /spl Delta//spl Sigma/ converter is presented. It uses a third-order 4-bit /spl Delta//spl Sigma/ topology with data weighted averaging (DWA) to reduce the linearity requirements of the digital-to-analog converters in the feedback loop. The implementation of the DWA algorithm is optimized to minimize the delay introduced in the feedback loop, resulting in clock frequencies up to 100 MHz. Behavioral models are used to determine several building block specifications. An… CONTINUE READING
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