A high performance FPGA implementation of DES

@article{McLoone2000AHP,
  title={A high performance FPGA implementation of DES},
  author={M{\'a}ire McLoone and John V. McCanny},
  journal={2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528)},
  year={2000},
  pages={374-383}
}
  • M. McLoone, J. McCanny
  • Published 11 October 2000
  • Computer Science
  • 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528)
FPGAs have proven to be very effective and efficient devices on which to implement encryption algorithms. They perform at much faster data-rates and provide better security than equivalent software implementations. They also provide more flexibility than ASIC implementations. This paper presents a high performance silicon intellectual property (IP) core for the data encryption standard (DES) encryption algorithm. The 16-stage pipelined DES design runs at an encryption rate of 3.87 Gbits/s using… 
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