A high performance 2.4 Mb L1 and L2 cache compatible 45nm SRAM with yield improvement capabilities

@article{Joshi2008AHP,
  title={A high performance 2.4 Mb L1 and L2 cache compatible 45nm SRAM with yield improvement capabilities},
  author={Rajiv V. Joshi and Raymond Houle and Daniel Rodko and Prachi Patel and W. Huott and R. Franch and Y. Chan and D. Plass and Scott Wilson and Shien-Yang Wu and Rouwaida Kanj},
  journal={2008 IEEE Symposium on VLSI Circuits},
  year={2008},
  pages={208-209}
}
A hardware based, fully functional, stable 2.4 Mb L1 and L2 Cache compatible 6T embedded SRAM is demonstrated. Measured results show an operating range of -40degC to 120degC, speed of 6.5 GHz and 3.8 GHz for L1-Cache cells and L2-Cache cells, respectively, at 1 V and 25degC, with high yield. The key features include multi-setting programmable clock block, separate read/write margin circuitry, low noise dynamic decoders, bit select circuitry supported by newly developed fast Monte Carlo… CONTINUE READING

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