A high performance 1.8 V, 0.20 /spl mu/m CMOS technology with copper metallization

@article{Venkatesan1997AHP,
  title={A high performance 1.8 V, 0.20 /spl mu/m CMOS technology with copper metallization},
  author={Sriram Venkatesan and A. V. Gelatos and B. Smith and R. Islam and Julia Cope and Benjamin Wilson and Dave Tuttle and Rob Cardwell and Stacie M. Anderson and M. Angyal and Rajeev Bajaj and C. Capasso and Pam J. Crabtree and S. Das and Julia Farkas and Stanley Filipiak and B. Fiordalice and M. R. Freeman and P. Gilbert and Michael Herrick and A. Jain and Hisao Kawasaki and Charles C. King and J. Klein and T. Lii and K. Reid and T. Saaranen and Cherie Simpson and Todd Sparks and P. Tsui and Ramnath Venkatraman and Dorraine Watts and E. Weitzman and Roger A. Woodruff and I. Yang and Navakanta Bhat and George Hamilton and Yi-qun Yu},
  journal={International Electron Devices Meeting. IEDM Technical Digest},
  year={1997},
  pages={769-772}
}
A high performance 0.20 /spl mu/m logic technology has been developed with six levels of planarized copper interconnects. 0.15 /spl mu/m transistors (L/sub gate/=0.15/spl plusmn/0.04 /spl mu/m) are optimized for 1.8 V operation to provide high performance with low power-delay products and excellent reliability. Copper has been integrated into the back-end… CONTINUE READING