A high performance 0.25 mu m CMOS technology

@article{Davari1988AHP,
  title={A high performance 0.25 mu m CMOS technology},
  author={B. Davari and W. Chang and M. Wordeman and C. Oh and Y. Taur and K. Petrillo and D. Moy and J. Bucchignano and H. Ng and M. Rosenfield and F. Hohn and M. Rodriguez},
  journal={Technical Digest., International Electron Devices Meeting},
  year={1988},
  pages={56-59}
}
A high-performance 0.25- mu m CMOS (complementary metal oxide semiconductor) technology with a reduced operating voltage of 2.5 V is presented. A loaded ring oscillator (NAND FI=FO=3. C/sub w/=0.2 pF) delay per stage of 280 ps achieved (W/sub eff//L/sub eff/=15 mu m/0.25 mu m), which is a 1.7 X improvement over 0.5- mu m CMOS technology. At shorter channel lengths (0.18 mu m), a CMOS stage delay of 38 ps for unloaded inverter ring oscillators and 185 ps for loaded NAND are demonstrated. A… Expand
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