A high-level synthesis and verification tool for application specific kth Root Processing Engine

@article{Aslan2013AHS,
  title={A high-level synthesis and verification tool for application specific kth Root Processing Engine},
  author={Semih Aslan and Hassan Salamy and Jafar Saniie},
  journal={2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)},
  year={2013},
  pages={1051-1054}
}
Implementation of division, square root, and cube root and their inverses at the hardware level creates a number of bottlenecks in terms of accuracy, speed and design verification in particular. There are many DSP and communication systems in which these arithmetic operations are used. Therefore, a Newton-Raphson algorithm based, efficient, accurate and reconfigurable kth root design and verification system is introduced. The design and verification system generates Verilog HDL design code and… CONTINUE READING

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