A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

@article{Fujiwara2016AHS,
  title={A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration},
  author={Koichi Fujiwara and Kazushi Kawamura and Masao Yanagisawa and Nozomu Togawa},
  journal={2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)},
  year={2016},
  pages={1-4}
}
High-level synthesis for FPGA designs (FPGA-HLS) is recently required in various applications. Since wire delays are becoming a design bottleneck in FPGA, we need to handle interconnection delays and clock skews in FPGA-HLS flow. In this paper, we propose an FPGA-HLS algorithm optimizing critical path with interconnection-delay and clock-skew consideration. By utilizing HDR architecture, we floorplan circuit modules in HLS flow and, based on the result, estimate interconnection delays and clock… CONTINUE READING

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SHOWING 1-8 OF 8 REFERENCES

A floorplan-driven highlevel synthesis algorithm utilizing interconnection delay characteristics in FPGA designs

K. Fujiwara, M. Yanagisawa, N. Togawa
  • Proc. of The 19th Workshop on Synthesis and System Integration of Mixed Information Technologies, pp. 224–225, 2015.
  • 2015
VIEW 10 EXCERPTS
HIGHLY INFLUENTIAL

Clock skew estimate modeling for FPGA high-level synthesis and its application

  • 2015 IEEE 11th International Conference on ASIC (ASICON)
  • 2015
VIEW 4 EXCERPTS
HIGHLY INFLUENTIAL

7 series FPGAs clocking resources

Xilinx User Guide
  • UG472, June 12, 2015.
  • 2015
VIEW 1 EXCERPT

Architecture and synthesis for on-chip multicycle communication

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2004
VIEW 1 EXCERPT

Forward-looking macro generation and relational placement during high level synthesis to FPGAs

  • 18th International Parallel and Distributed Processing Symposium, 2004. Proceedings.
  • 2004
VIEW 1 EXCERPT

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