• Corpus ID: 9164526

A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates

@article{Chowdhury2008AHS,
  title={A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates},
  author={Shubhajit Roy Chowdhury and Aritra Banerjee and Aniruddha Roy and Hiranmay Saha},
  journal={World Academy of Science, Engineering and Technology, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering},
  year={2008},
  volume={2},
  pages={2244-2250}
}
  • S. R. Chowdhury, A. Banerjee, H. Saha
  • Published 29 October 2008
  • Engineering
  • World Academy of Science, Engineering and Technology, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering
The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15 m and 0.35 m technologies. Compared to the earlier designed 10 transistor full… 

A High Speed Full Adder Circuit using 3 Transistor XOR Gates for Arithmetic Operations of VLSI System

TLDR
The proposed adder gives better propagation delay in comparison with the previously existing reference design and the complete design is simulated with the help of LTSPICE.

CMOS Based 1-Bit Full Adder Cell for Low-Power Delay Product

The 1-bit full adder circuit is one of the most important components of any digital system applications. The power-delay product is a measurement of the energy expanded per operational cycle of an

Low Power 14T Hybrid Full Adder Cell

TLDR
A new hybrid 1-bit 14 transistor full adder design is proposed using pass gate as well as CMOS logic hence named hybrid, which remarkably improves the power consumption, power-delay product and has less parasitic capacitance when compared to the 16T design.

One Bit 8T Full Adder Circuit Using 3T XOR Gate and One Multiplexer

TLDR
This paper contributes to better understanding of the behavior of single bit full adder cell by using suit and simulation using 70nm CMOS technology to obtain of the performance of the cell with respect to time and power consumption.

PMOS based 1-Bit Full Adder Cell

TLDR
The proposed design demonstrates its superiority against existing adder in terms of power–delay product, temperature sustainability and noise immunity, and shows remarkable improvement in threshold loss as compared to existing 8T full adder for certain input combinations.

Design of a novel low power 8-transistor 1-bit full adder cell

TLDR
The results show that the proposed adder has both lower power consumption and a lower power-delay product (PDP) value, which make the novel 8T full adder cell a candidate for power-efficient applications.

Ultra low-power high-speed single-bit hybrid full adder circuit

  • Manoj KumarR. Baghel
  • Engineering
    2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT)
  • 2017
In this paper a low power hybrid 1-bit full adder circuit is designed and extended for 4 bit ripple carry adder (RCA). A new XNOR logic is designed using complimentary-metal-oxide semiconductor

Low Power Full Adder With Reduced Transistor Count

TLDR
A new eight transistors one bit full adder based on 3T-XOR gate based on standard 90nm CMOS technology is presented with a significant improvement in terms of number of transistors, chip area and propagation delay.

A High Speed and Low Power 8 Bit x 8 Bit Multiplier Design using Novel Two Transistor ( 2 T ) XOR Gates

The paper proposes a novel design of two transistor (2T) XOR gate and its application to design an 8 bit x 8 bit multiplier. The design explores the essence of suitably biasing the MOS transistor and

Design and Analysis of 8T Full Adder Cell Using Double Gate MOSFET

This paper presents a design of a 8 transistor one- bit full adder cell with Double Gate MOSFET. This design has been compared with existing 8 transistor one-bit full adder cell using Single Gate
...

References

SHOWING 1-10 OF 31 REFERENCES

Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates

TLDR
This paper proposes a technique to build a total of 41 new 10-transistor full adders using novel XOR and XNOR gates in combination with existing ones to reduce the threshold-voltage loss of the pass transistors.

The novel efficient design of XOR/XNOR function for adder applications

  • Kuo-Hsing ChengChih-Sheng Huang
  • Engineering
    ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357)
  • 1999
TLDR
A new concept to implement high performance XOR/XNOR functions that using the pass transistor technique is proposed, which requires only six MOS transistors and shows that the proposed new circuit has the lowest power delay product performance.

Design and analysis of 10-transistor full adders using novel XOR-XNOR gates

  • H. BuiA. Al-SheraidahYuke Wang
  • Engineering
    WCC 2000 - ICSP 2000. 2000 5th International Conference on Signal Processing Proceedings. 16th World Computer Congress 2000
  • 2000
TLDR
A technique to build a total of 41 new 10-transistor full adders using novel XOR and XNOR gates in combination with existing ones is proposed, which consume less power in high frequencies, while three new adders consistently consume on average 10% less power and have higher speed.

A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design

TLDR
The proposed design successfully embeds the buffering circuit in the full adder design and the transistor count is minimized, and has the lowest working Vdd and highest working frequency among all designs using ten transistors.

A 14-transistor CMOS full adder with full voltage-swing nodes

  • M. Vesterbacka
  • Engineering
    1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)
  • 1999
TLDR
It is explained how exclusive OR and NOR circuits (XOR/XNOR) are used to realize a general full adder circuit based on pass transistors, which is realized using only 14 MOSFETs, while having full voltage-swing in all circuit nodes.

A low power 10-transistor full adder cell for embedded architectures

  • A. FayedM. Bayoumi
  • Engineering
    ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)
  • 2001
TLDR
A high performance Full adder cell has been designed using 10 transistors that has the advantage of low power consumption and high operating speed and is compared with both the standard Transmission Gate addercell and a 16-transistor adder Cell that was recently developed and characterized by its low power consume compared to other adder cells.

Low-voltage low-power CMOS full adder

Low-power design of VLSI circuits has been identified as a critical technological need in recent years due to the high demand for portable consumer electronics products. In this regard many

An area-efficient static CMOS carry-select adder based on a compact carry look-ahead unit

New 4-transistor XOR and XNOR designs

TLDR
A new set of low power 4-transistor XOR/XNOR gates is proposed, which consumes up to more than 3 times less power than the complementary CMOS implementation and can have 34% better propagation delay.

A novel low power energy recovery full adder cell

TLDR
The proposed SERF adder design was proven to be superior to the other three designs in power dissipation and area, and second in propagation delay only to the DVL adder.