Corpus ID: 9164526

A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates

@article{Chowdhury2008AHS,
  title={A high Speed 8 Transistor Full Adder Design Using Novel 3 Transistor XOR Gates},
  author={S. Chowdhury and A. Banerjee and Aniruddha Roy and H. Saha},
  journal={World Academy of Science, Engineering and Technology, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering},
  year={2008},
  volume={2},
  pages={2244-2250}
}
  • S. Chowdhury, A. Banerjee, +1 author H. Saha
  • Published 2008
  • Computer Science
  • World Academy of Science, Engineering and Technology, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering
  • The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15 m and 0.35 m technologies. Compared to the earlier designed 10 transistor full… CONTINUE READING
    106 Citations
    A High Speed Full Adder Circuit using 3 Transistor XOR Gates for Arithmetic Operations of VLSI System
    • Highly Influenced
    • PDF
    CMOS Based 1-Bit Full Adder Cell for Low-Power Delay Product
    • 12
    Low Power 14T Hybrid Full Adder Cell
    • 2
    PMOS based 1-Bit Full Adder Cell
    • 7
    Design of a novel low power 8-transistor 1-bit full adder cell
    • Y. Wei, J. Shen
    • Computer Science
    • Journal of Zhejiang University SCIENCE C
    • 2011
    • 28
    Ultra low-power high-speed single-bit hybrid full adder circuit
    • M. Kumar, R. Baghel
    • Computer Science
    • 2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT)
    • 2017
    • 4
    Low Power Full Adder With Reduced Transistor Count
    • 14
    Design Of Area Efficient And Low Power 4-Bit Multiplier Based On Full- swing GDI technique
    • 2
    • PDF

    References

    SHOWING 1-10 OF 33 REFERENCES
    The novel efficient design of XOR/XNOR function for adder applications
    • K. Cheng, Chih-Sheng Huang
    • Computer Science
    • ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357)
    • 1999
    • 39
    Design and analysis of 10-transistor full adders using novel XOR-XNOR gates
    • H. Bui, A. Al-Sheraidah, Yuke Wang
    • Computer Science
    • WCC 2000 - ICSP 2000. 2000 5th International Conference on Signal Processing Proceedings. 16th World Computer Congress 2000
    • 2000
    • 72
    A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design
    • 225
    A 14-transistor CMOS full adder with full voltage-swing nodes
    • M. Vesterbacka
    • Computer Science
    • 1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)
    • 1999
    • 131
    A low power 10-transistor full adder cell for embedded architectures
    • A. Fayed, M. Bayoumi
    • Engineering, Computer Science
    • ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)
    • 2001
    • 90
    Low-voltage low-power CMOS full adder
    • 311
    New 4-transistor XOR and XNOR designs
    • H. Bui, A. Al-Sheraidah, Yuke Wang
    • Computer Science
    • Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)
    • 2000
    • 92
    A novel low power energy recovery full adder cell
    • 238
    • PDF