A hierarchical pipelining architecture and FPGA implementation for lifting-based 2-D DWT


Numerous VLSI architectures for 2-D discrete wavelet transform (DWT) have been brought forward. While most of the designs displayed good performance through parallel processing, few of them addressed thoroughly how to sustain such high throughput computing which is crucial in real-time applications. Although the affordable data transfer bandwidth has been… (More)
DOI: 10.1007/s11554-007-0057-6


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