A hardware-efficient architecture for embedded real-time cascaded support vector machines classification

@inproceedings{Kyrkou2013AHA,
  title={A hardware-efficient architecture for embedded real-time cascaded support vector machines classification},
  author={Christos Kyrkou and Theocharis Theocharides and Christos-Savvas Bouganis},
  booktitle={ACM Great Lakes Symposium on VLSI},
  year={2013}
}
This work presents an optimized architecture for cascaded SVM processing, along with a hardware reduction method for the implementation of the additional stages in the cascade, leading to significant improvements. The architecture was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640×480 resolution images. Additionally, it was compared against implementations of the same cascade processing architecture but without using the reduction… CONTINUE READING