A hardware design of MS/MMS-based LDPC decoder

This paper presents a hardware design of a LDPC decoder where Min-Sum (MS) and Modified Min-Sum (MMS) algorithm has been investigated. The parity check matrix is complied with IEEE 802.11n recommendation (code rate of 0.5, 648 bits block length). Verilog description language is employed for Xilinx XC2VP30-7 FPGA. With the matrix reordering technique, the… CONTINUE READING