• DOI:10.1109/ISQED.2001.915206
Corpus ID: 10354958

A hardware and software monitor for high-level system-on-chip verification

@article{Shobaki2001AHA,
  title={A hardware and software monitor for high-level system-on-chip verification},
  author={Mohammed El Shobaki and L. Lindh},
  journal={Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design},
  year={2001},
  pages={56-61}
}

Mohammed El Shobaki, L. Lindh

Published 2001

Computer Science

Proceedings of the IEEE 2001. 2nd International Symposium on Quality Electronic Design

Verification of today's Systems-on-Chip (SoC) occurs at low abstraction-levels, typically at register-transfer level (RTL). As the complexity of SoC designs grows, it is increasingly important to move verification to higher abstraction-levels. Hardware/software co-simulation is a step in this direction, but is not sufficient due to inaccurate processor models, and slow hardware simulation speeds. System-level monitoring commonly used for event-based software debugging, provides information… CONTINUE READING

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