A hard real-time capable multi-core SMT processor

@article{Paolieri2013AHR,
  title={A hard real-time capable multi-core SMT processor},
  author={Marco Paolieri and J{\"o}rg Mische and Stefan Metzlaff and Mike Gerdes and Eduardo Qui{\~n}ones and Sascha Uhrig and Theo Ungerer and Francisco J. Cazorla},
  journal={ACM Trans. Embedded Comput. Syst.},
  year={2013},
  volume={12},
  pages={79:1-79:26}
}
Hard real-time applications in safety critical domains require high performance and time analyzability. Multi-core processors are an answer to these demands, however task interferences make multi-cores more difficult to analyze from a worst-case execution time point of view than single-core processors. We propose a multi-core SMT processor that ensures a bounded maximum delay a task can suffer due to inter-task interferences. Multiple hard real-time tasks can be executed on different cores… CONTINUE READING
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