A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation

@article{Mui2004AGI,
  title={A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation},
  author={Man Lung Mui and Krishnadas Banerjee and Amit K. Mehrotra},
  journal={IEEE Transactions on Electron Devices},
  year={2004},
  volume={51},
  pages={195-203}
}
This paper addresses the critical problem of global wire optimization for nanometer scale very large scale integration technologies, and elucidates the impact of such optimization on power dissipation, bandwidth, and performance. Specifically, this paper introduces a novel methodology for optimizing global interconnect width, which maximizes a novel figure of merit (FOM) that is a user-defined function of bandwidth per unit width of chip edge and latency. This methodology is used to develop… CONTINUE READING
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