A fully automated large-scale addressable test chip design with high reliability

Abstract

During the development of modern semiconductor processes, which has increasing complexity and an extremely high number of degrees of freedom, a large number of distinct test structures are required to test and ensure the yield and manufacturability. To increase the utilization of chip area, addressable methodology of test chip is developed. In this paper… (More)
DOI: 10.1109/ECCTD.2011.6043609

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