A fully Synchronous Circuit design for embedded DRAM

@article{Yamazaki1996AFS,
  title={A fully Synchronous Circuit design for embedded DRAM},
  author={Akira Yamazaki and Naoji Okumura and Katsumi Dosaka and Masaki Kumanoya},
  journal={ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference},
  year={1996},
  pages={380-383}
}
A fully synchronous circuit for embedded DRAMs is presented. It realizes accurate DRAM timing control, and easy timing adjustment. Using the circuit, software switching of the control timing is realized without difficulty. Providing handshake signals to on-chip memory-controller simplifies the memory-controller circuit in a CPU embedded DRAM.