A framework for layout-level logic restructuring

It is well known that optimizations made by traditional logic synthesis tools often correlate poorly with post-layout performance; this is largely a result of interconnect effects only visible after layout. As a result, several attempts at physically aware logic synthesis have been made (e.g.,[2], [9], [14], [4], [7], [12], [16], [15]). In this paper a… CONTINUE READING