A framework for VHDL combining theorem proving and symbolic simulation

@inproceedings{Georgelin2002AFF,
  title={A framework for VHDL combining theorem proving and symbolic simulation},
  author={Philippe Georgelin and Dominique Borrione and P. Ostier},
  year={2002}
}
We present the status of an on-going work aiming at introducing symbolic simulation and theorem proving in a design flow that uses conventional description and simulation languages. This paper focuses on the formalization of the cycle simulation semantics of a synchronous subset of VHDL, in the ACL2 logic. The model is executable, and the results of its symbolic simulation can be proven equal to a specified expression. The ACL2 input is produced automatically from the VHDL source, which… CONTINUE READING

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