A fractional-NBB-DPLL with auto-tuned DTC and FIR filter for noise and spur reduction

Abstract

A 16-modulo fractional-N bang-bang digital PLL (BB-DPLL) is implemented in 65nm CMOS. It is firstly shown that a hybrid FIR filtering method not only improves spur performance but also reduces in-band phase noise for finite-modulo fractional-N bang-bang PLLs. A 4-bit digital-to-time converter (DTC) with auto-tuned delay cells is also employed to further… (More)

9 Figures and Tables

Cite this paper

@article{Liu2017AFW, title={A fractional-NBB-DPLL with auto-tuned DTC and FIR filter for noise and spur reduction}, author={Han Liu and Sitao Lv and Xiaohua Huang and Woogeun Rhee and Zhihua Wang}, journal={2017 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)}, year={2017}, pages={238-240} }