A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations

@article{Kim2005AFB,
  title={A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations},
  author={Chris H. Kim and Jae-Joon Kim and Saibal Mukhopadhyay and Kaushik Roy},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2005},
  volume={13},
  pages={349-357}
}
This paper presents a forward body-biasing (FBB) technique for active and standby leakage power reduction in cache memories. Unlike previous low-leakage SRAM approaches, we include device level optimization into the design. We utilize super high Vt (threshold voltage) devices to suppress the cache leakage power, while dynamically FBB only the selected SRAM cells for fast operation. In order to build a super high Vt device, the two-dimensional (2-D) halo doping profile was optimized considering… CONTINUE READING
Highly Cited
This paper has 99 citations. REVIEW CITATIONS

16 Figures & Tables

Topics

Statistics

051015'06'07'08'09'10'11'12'13'14'15'16'17'18
Citations per Year

100 Citations

Semantic Scholar estimates that this publication has 100 citations based on the available data.

See our FAQ for additional information.