A formal verification technique for embedded software

  title={A formal verification technique for embedded software},
  author={Olivier Thiry and Luc J. M. Claesen},
A method for the verification of embedded software correctness is presentedl. A formal model for an actual commercial microprocessor is established. This is done by modeling the instruction set and processor architecture. Embedded software takes the form of the assembly program code to be run on the processor. Specifications are given as CTL temporal logic formulae. The method has been implemented in the SMV model checker and is illustrated by a practical embedded system application: a mouse… CONTINUE READING