A formal verification method of scheduling in high-level synthesis

  title={A formal verification method of scheduling in high-level synthesis},
  author={Chandan Karfa and Chittaranjan A. Mandal and Dipankar Sarkar and Sri Ram Pentakota and Chris Reade},
  journal={7th International Symposium on Quality Electronic Design (ISQED'06)},
  pages={6 pp.-78}
This paper describes a formal method for checking the equivalence between the finite state machine with data path (FSMD) model of the high-level behavioural specification and the FSMD model of the behaviour transformed by the scheduler. The method consists in introducing cutpoints in one FSMD, visualizing its computations as concatenation of paths from cutpoints to cutpoints and finally, identifying equivalent finite path segments in the other FSMD; the process is then repeated with the FSMDs… CONTINUE READING
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High- Level Synthesis: Introduction to Chip and System Design

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