A folded-channel MOSFET for deep-sub-tenth micron era

@article{Hisamoto1998AFM,
  title={A folded-channel MOSFET for deep-sub-tenth micron era},
  author={Digh Hisamoto and Wen-Chin Lee and Jakub Kedzierski and Erik H. Anderson and Hideki Takeuchi and K. Asano and Tsu-Jae King and Jeffrey Bokor and Chenming Hu},
  journal={International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)},
  year={1998},
  pages={1032-1034}
}
Deep-sub-tenth micron MOSFETs with gate length down to 20 nm are reported. To improve the short channel effect immunities, a novel folded channel transistor structure is proposed. The quasi-planar nature of this new variant of the vertical double-gate SOI MOSFETs simplified the fabrication process. The special features of the structure are: (1) a transistor is formed in a vertical ultra-thin Si fin and is controlled by a double-gate, which suppresses short channel effects; (2) the two gates are… 

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