A floorplan-aware high-level synthesis technique with delay-variation tolerance

@article{Kawamura2015AFH,
  title={A floorplan-aware high-level synthesis technique with delay-variation tolerance},
  author={Kazushi Kawamura and Yuta Hagio and Youhua Shi and Nozomu Togawa},
  journal={2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC)},
  year={2015},
  pages={122-125}
}
For realizing better trade-off between performance and yield rate in recent LSI designs, it is required to deal with increasing the ratios of interconnect delay as well as delay variation. In this paper, a novel floorplan-aware high-level synthesis technique with delay-variation tolerance is proposed. By utilizing floorplan-driven architectures, interconnect delays can be estimated and then handled even in high-level synthesis. Applying our technique enables to realize two scheduling/binding… CONTINUE READING

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SHOWING 1-6 OF 6 REFERENCES

An energy-efficient patchable accelerator for postsilicon engineering changes

H. Yoshida
  • Proc. of the 9th International Conference on Hardware/Software Codesign and System Synthesis, pp. 13–20, 2011. 2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) 125
  • 2011

Architecture and synthesis for on-chip multicycle communication

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • 2004
VIEW 2 EXCERPTS

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