A field programmable neural array

@article{Farquhar2006AFP,
  title={A field programmable neural array},
  author={Ethan David Farquhar and Christal Gordon and Paul E. Hasler},
  journal={2006 IEEE International Symposium on Circuits and Systems},
  year={2006},
  pages={4 pp.-4117}
}
An analog circuit capable of accurately emulating large complex cells, or multiple less complex ones is described. This circuit is termed the FPNA or the field programmable neural array. It is analogous to the more familiar FPGA, but is composed of biologically relevant circuit components including active channels, dendrites, and synapses. Taking each of these circuit models, and adding a routing structure capable of routing outputs from cells (or external inputs) to any individual synapse at… 

Figures from this paper

An Implementation of a Biological Neural Model using Analog-Digital Integrated Circuits
TLDR
The hardware implementation focuses on modeling the behavior of two-cells, PD-LP system of a Pyloric Network from a lobster's stomach, which emulates, in real-time, a digital representation of interacting neurons whose biological behavior is known.
Building large networks of biological neurons
TLDR
Recent results on voltage-clamp measurements for Silicon Sodium and Potassium Channels, biologically realistic action potentials from these channels, models of programmable and learning synapses with biological responses, and active models of dendritic cables are presented.
Programmable Analog VLSI Architecture Based upon Event Coding
A programmable analog array inspired from neuronal spike event coding is presented. A configurable event block forms the basic building block of the programmable array. The internal circuit
DANNA A Neuromorphic Computing VLSI Chip
TLDR
A semi-custom Very Large Scale Integration (VLSI) implementation has been created that improves upon the FPGA implementation in three key areas and allows for near real time monitoring of the individual elements in the array.
Development of a multi-compartment neuron model emulation
TLDR
This work describes the design of an analog circuit emulating a multi-compartment neuron model on a microchip with capabilities of reproducing biological neuron’s behavior and the influence of fixed-pattern noise on the circuit.
A Programmable Time Event Coded Circuit Block for Reconfigurable Neuromorphic Computing
TLDR
A generic programmable time event coded circuit which forms the building block for a reconfigurable neuromorphic array is implemented in analog VLSI and functional circuit blocks of a spike time based neuromorphic model are implemented.
Bio-inspired Event Coded Configurable Analog Circuit Block
TLDR
An event coded configurable analog circuit block that forms the building block of a programmable analog array is presented, inspired from the behavior of biological neurons that process signals in analog domain and transmit them as spike events.
Hardware implementation of spiking neural networks on FPGA
TLDR
A hardware implementation of SNN based on Field-Programmable Gate Arrays (FPGA) features a hybrid updating algorithm, which combines the advantages of existing algorithms to simplify hardware design and improve performance.
Scalable event-driven modelling architectures for neuromimetic hardware
TLDR
Experiments demonstrate the capability of the library model to implement efficient on-chip neural networks, but also reveal importanthardware limitations, particularly with respect to communications, that require careful design.
...
...

References

SHOWING 1-10 OF 11 REFERENCES
A spiking silicon central pattern generator with floating gate synapses [robot control applications]
TLDR
The patterns generated by these circuits are shown to be sufficient to control a biped robot with a variety of different locomotory gaits and to show how elaborate and biologically-plausible CPG networks can be implemented by controlling synaptic weights.
An artificial synapse for interfacing to biological neurons
TLDR
CMOS, bio-inspired circuits that are used to link an artificial neuron and a living neuron and between two living neurons are detailed and can be viewed as similar to LTP and LTD.
A family of floating-gate adapting synapses based upon transistor channel models
TLDR
A family of three analog VLSI synapses based on three types of biological channel types, Ach-excitatory, NMDA-exciting, and GABA/sub A/-inhibitory in a 0.5 /spl mu/m CMOS process is developed and EPSPs and IPSPs similar to what is found in biology are reproduced.
A neuromorphic IC connection between cortical dendritic processing and HMM classification
TLDR
Using floating-gate transistors, this work is able to individually vary the conductance of each diffuser element in the array, which dramatically changes the analysis of these arrays.
A bio-physically inspired silicon neuron
TLDR
This circuit operates in real-time, is fabricated on standard CMOS processes, runs in subthreshold, and has a power supply similar to that of real biology.
A VLSI reconfigurable network of integrate-and-fire neurons with spike-based learning synapses
TLDR
The results indicate that these circuits can be reliably used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning al- gorithms.
Biological learning modeled in an adaptive floating-gate system
  • C. Gordon, P. Hasler
  • Computer Science, Biology
    2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353)
  • 2002
TLDR
This paper explores the relationship between synaptic activity and weight for various inputs and uses a relatively simple network to bootstrap into larger, more complex systems.
Developing large-scale field-programmable analog arrays for rapid prototyping
TLDR
By leveraging recent advances in floating gate transistors, a new generation of FPAAs are achievable that will dramatically advance the current state of the art in terms of size, functionality, and flexibility.
Automatic rapid programming of large arrays of floating-gate elements
  • G. Serrano, Paul D. Smith, P. Hasler
  • Computer Science, Engineering
    2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
  • 2004
TLDR
This paper presents a system approach that allows for automatic rapid programming of large arrays of floating-gates by optimizing all the time consuming tasks involved in the programming, such as current measurements and drain pulsing among others.
A reconfigurable bidirectional active 2 dimensional dendrite model
TLDR
A 2 dimensional diffuser array is described which provides a general model for implementing and studying dendrites with an arbitrary arborization pattern, makes use of floating gate transistors for biasing, and has provided some promising results.
...
...