A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)

@inproceedings{Sasan2009AFT,
  title={A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)},
  author={Avesta Sasan and Houman Homayoun and Ahmed M. Eltawil and Fadi J. Kurdahi},
  booktitle={CASES},
  year={2009}
}
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of Manufacturing Process Variation induced defects. Based on a smart relocation methodology, RDC-Cache decomposes the data that is targeted for a defective cache way and relocates one or few word to a new location avoiding a write to defective bits. Upon a read request, the requested data is recomposed through an inverse… CONTINUE READING
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